1. Field of the Invention
The present invention relates to memory devices. More particularly, this invention relates to controlling the access to such memory devices.
2. Description of the Prior Art
FIG. 1 schematically illustrates a known data processing apparatus which is embodied as a system-on-chip (SoC) device 10. Within this SoC device 10 are provided a processor unit (CPU) 11 and two memory banks 12 and 13. The CPU 11 uses the memory banks 12 and 13 to store data which it makes use of in its data processing operations. The CPU 11 accesses the memory banks 12 and 13 via a system bus 14 which couples these components together. The CPU 11 is configured to issue a memory access request onto the system bus 14 when it requires access (whether read or write) to data stored in one of the memory banks. As schematically illustrated in FIG. 1, the CPU 11 therefore passes an address onto the system bus and sends or receives (depending on whether the memory access request is a read or a write operation) data to/from the system bus. Each memory bank 12, 13 is respectively provided with a control unit 15, 16 which administers overall control of the respective memory bank, in particular interpreting the address received from the CPU 11 via the system bus 14 to cause the correct storage locations within the memory bank (typically configured as an array of bit cells) to be accessed.
The CPU 11 is additionally configured to generate a chip select signal which is also passed via the system bus 14 to the memory banks 12, 13. This chip select signal acts as an overall enable signal with respect to the memory banks, and causes the entire memory bank to be powered up or powered down. The chip select signal may serve to indicate which of the memory banks 12, 13 the address passed from the CPU 11 should be applied to, for example in the situation where each memory bank covers the same address space and therefore the chip select signal is required to distinguish between the two. Even if there is no overlap in the memory spaces used by the two memory banks, it is generally desirable in a SoC device to reduce its power consumption as far as possible and accordingly the CPU 11 can make use of the chip select signal to power down a memory bank which is not currently in use. The control units 15, 16 of the memory banks 12, 13 are therefore configured to respond to the assertion of a chip select signal identifying that particular memory bank by causing it to power up or power down as appropriate. Whilst this technique is advantageous in terms of the power saving advantages it brings, the process of powering up/powering down a memory bank comes at the cost of some delay whilst this is carried out.
It would be desirable to provide an improved technique for reducing the power consumption of such memory devices.